Which rung this is on
zHBM stacks high bandwidth memory vertically above the AI accelerator, which shortens the distance data travels compared with placing it alongside the processor. Samsung showed it at FMS 2026 together with zNAND-O and a V10 BV-NAND built on more than 400 layers, and described zHBM and zNAND-O as concept models.[1]
Concept model is a precise phrase and it belongs at the bottom of the ladder that runs from promise to contract, construction, shipment, energisation and workload. No commercialisation date and no price accompanied it. The V10 BV-NAND is the one item on a different rung: it raises density by about 58 percent over the V9 generation using a new wafer bonding technology, and that comparison holds two named product generations against each other.[1]
What the multipliers are missing
Samsung says a next-generation interface system incorporating zHBM is expected to deliver about 8 times the performance of HBM5, more than 10 times its memory density and 3 times its energy efficiency, and to reduce thermal resistance by more than half. Put those on a denominator and the denominator is not there. Performance of what workload, at what precision, at what utilisation, inside which cooling boundary?[1]
Density and thermal resistance are the two figures I would expect to survive scrutiny first, because they are properties of the stack itself, and running a job does not change them. Performance and energy efficiency depend on what the accelerator is doing, and against an unshipped comparison generation they remain a vendor expectation. The company's own wording keeps that distinction: the system is expected to deliver these figures.[1]
The part a buyer would sign
The customisation detail is the most operationally concrete thing in the announcement. zHBM supports customer-specific designs, with customised blocks placed in the interlayer between memory and accelerator. That is an engagement model, and it implies co-design lead time, a shared thermal budget and a commitment on both sides well before any wafer starts.[1]
The keynote was delivered by Jin-Yub Lee, executive vice president and head of Flash Product & Technology, and Kyungryun Kim, vice president and project leader of the DRAM design team. The signal that would move zHBM up a rung is a named accelerator partner with an interlayer specification, or a stated sampling quarter of the kind the V10 BV-NAND generation comparison already carries.[1]