d-Matrix announced a multi-year collaboration that will place its next-generation Raptor XPU in Nvidia's MGX rack architecture through NVLink Fusion. The company targets tape-out before the end of 2026, while StorageReview reports that the first rack systems are targeted for the fourth quarter of 2027. The partnership puts the custom inference chip in one architecture with established networking, CPU and rack components.
d-Matrix says it will connect Raptor inference XPUs to Nvidia's MGX reference architecture with NVLink Fusion. The planned rack combines Vera CPUs, NVLink switches, BlueField-4 DPUs, ConnectX-9 SuperNICs and Spectrum-X Ethernet. The company presents this as the center of a multi-year product roadmap. Raptor remains under development: tape-out is expected before the end of 2026, and that milestone does not mean volume production has begun.[1], [2]
According to the vendor announcement, Raptor combines a 3-dimensional DRAM stack with an SRAM compute chip in one package. The design aims to keep model weights and intermediate data closer to computation during large-language-model inference. d-Matrix also says hyperscalers and frontier AI labs are evaluating Raptor. Those technical and commercial statements come from the company; the announcement provides no independent comparative results for latency, energy use or total cost of ownership.[1]
StorageReview reports that the first Raptor-MGX rack systems are targeted for the fourth quarter of 2027. It frames the value of the deal not only around chip features but around the possibility of reducing integration time and risk through Nvidia's established rack and networking ecosystem. The announced product is therefore not a rack shipping today; it is a roadmap that must pass tape-out, validation, manufacturing and system integration. Performance claims can be tested when measurements from final hardware are published.[2]
