Kyoto team scales SiC transistors to a 150 mm wafer
Kyoto University and Phenitec Semiconductor moved two silicon-carbide transistor types from small samples onto a 150 mm wafer in an industrial plant. Threshold voltage varied little across its central 90 mm. That advances fabrication of multiple devices together, but the announcement gives no matching uniformity figure for the whole wafer and shows no working integrated circuit. The results were presented at a conference and have not appeared in a journal.
Science··Midday
A factory wafer replaces small samples
Kyoto University researchers worked with Phenitec Semiconductor to make silicon-carbide junction field-effect transistors in an industrial fabrication plant. The team transferred much of its earlier process from small laboratory samples to a 150 mm wafer, where both n-type and p-type devices were fabricated and checked for operation. Producing many small transistors together matters for an eventual integrated circuit; the previous work had instead established a device structure that could operate at 600 °C. This announcement concerns manufacturing scale, not a higher temperature record.[1]
The narrow result is at the centre
In the central 90 mm region, threshold voltage had a standard deviation below 0.07 V. Threshold voltage is the point at which a transistor begins to conduct, so variation between devices matters when they must work together in a circuit. The announcement gives no comparable numerical uniformity result for the outer part or the whole wafer. Mitsuaki Kaneko said the central uniformity surprised the team during its first fabrication trial. That measurement is promising, but it does not show a completed integrated circuit.[1]
Applications remain a future step
Kyoto University names Venus exploration, geothermal work and sensors in jet engines as possible future uses of high-temperature circuitry. None is a demonstrated application of this wafer. The work was presented in Yokohama at a silicon-carbide meeting; it has yet to appear in a journal. The practical gap is clear: a successful central-wafer measurement must be followed by circuit fabrication and performance tests before the proposed harsh-environment uses can be assessed.[1]
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