A layer assembled from carbon dots enabled researchers to grow thin insulating films on two-dimensional semiconductors. In one peer-reviewed study, the interface supported small logic circuits operating at low voltage. Growing the oxide without covalently changing the channel addresses a fabrication difficulty for atomically thin electronics. Gate failure occurred more frequently with the thinnest insulation, leaving a tradeoff between thickness and the proportion of functioning devices.
Carbon dots used to grow thin insulation on two-dimensional semiconductors supported the construction of small low-voltage circuits. In one peer-reviewed experimental study, the team used three transistors for an inverter and five for a NOR logic gate. A supply voltage of 0.5 V operated both circuits. The approach joined the deposition of insulation above an atomically thin channel with its use in functioning circuits.[1]
Smooth semiconductor surfaces offer few dangling bonds to start oxide growth. Atomic layer deposition can consequently form disconnected islands instead of a continuous film. The researchers arranged carbon dots in one layer, using particles approximately 1–5 nm across and derived from coal. Chemical groups at the edges provide oxide nucleation sites, while the flat surfaces interact with the channel by van der Waals forces. This permits dielectric growth without covalently modifying the channel.[1]
A physical thickness of approximately 0.4 nm was measured for the carbon layer. Depositing hafnium oxide at 1.6 nm above it gave a value of 0.6 ± 0.1 nm for equivalent oxide thickness. Equivalent thickness is an electrical measure comparing capacitance with silicon dioxide; the physical film thickness is a separate quantity.[1]
With 3 nm hafnium oxide on molybdenum disulfide arrays, more than 90 per cent of devices avoided gate failure. The thinnest option had a higher failure rate. Threshold shifts remained below 25 mV during two hours of bias-stress testing. The demonstration covers small circuits and short electrical stress tests; processor-scale manufacturing and commercial operating lifetime remain unverified.[1]
