Eigen RadarScience
Archive
Analysis

A double p-layer power transistor improves the voltage–resistance balance in simulation

A vertical power transistor design using two p-type layers redistributed the electric field in computer simulations. One peer-reviewed engineering study examined the competing goals of sustaining voltage while switched off and limiting resistance while conducting. Changing layer width and doping helped model charge balance. Voltage and resistance figures for the proposed architecture are simulation results, with the modeling approach calibrated against earlier experimental data; they are not measurements of a newly fabricated chip.

Science··Evening
A black power transistor with three metal leads rests on an antistatic mat on a pale workbench, with a tool tray and the back of a monitor behind.

Simulation assesses voltage and conducting resistance together

A design incorporating two p-type layers into a vertical power transistor improved the voltage–resistance balance in simulation. One peer-reviewed engineering study calculated a breakdown voltage of 78.6 V and a specific on-state resistance of approximately 0.39 mΩ cm² for the proposed structure. These results belong to the computer model of the new design. Sustaining voltage when switched off and conducting with low resistance when switched on are competing requirements in power transistors.[1]

The proposal reshapes the electric field in a metal-oxide-semiconductor field-effect transistor, or MOSFET. A drift region capable of sustaining higher voltage often brings increased conducting resistance. The structure addresses that balance through layer charges that reduce concentrated electric fields.[1]

An added p layer sits in the drift region

One layer sits in the drift region and another lies between laterally arranged gates. The researchers changed the added layer’s width, doping and gate geometry to investigate charge balance between p-type and n-type regions. The preferred width ratio in the model was 1.5. Electric-field profiles illustrate how balanced charges can spread the field.[1]

Earlier experimental data calibrate the model

The calculations used two-dimensional Silvaco ATLAS semiconductor simulations, calibrated against previously published experimental data. Gate charge and gate-to-drain capacitance were calculated to assess switching behavior. A possible sequence of fabrication steps was described. Production yield, operating lifetime under heat and switching losses in hardware for the proposed architecture remain awaiting experimental validation.[1]

References

  1. News sourceScientific ReportsHigh-performance charge balanced double p-layer double lateral gate vertical power MOSFET
    Primary paperScientific ReportsHigh-performance charge balanced double p-layer double lateral gate vertical power MOSFET
    ↩1↩2↩3↩4
Space and explorationEnergy transition and climate

More analysis from this desk

View all Brief analyses from the Science desk →